Electronic multiselector

ABSTRACT

An electronic multiselector employs metal-oxide-silicon FET transistors in logic circuits comprising NOR gates and inverters. Horizontal selection signals are delivered by a shift register which provides line scanning in a selection stage.

Uite States Patent Pierre Girard Paris;

Marc Jean Pierre Leger, lssy-Les- Moulineaux; Claude Paul Henri Lerouge, Maurepas (Yvelines); Jacques Henri De Jean, Ris-Orangis, all of, France 172] inventors [21] Appl. No, 819,700

[22] Filed Apr. 28, 1969 [451 Patented July 13, 1971 [73] Assignee International Standard Electric Corporation New York, N.Y.

[32] Priority Apr. 30, 1968 [3 3 1 France [54] ELECTRONIC MULTISELECTOR 4 Claims, 4 Drawing Figs.

[52] US. Cl 340/166, I 179/18 GF [51] Int. Cl H04q 9/00 F T "l [50] FieldofSearch .1 340/166; 179/18.7YA,18 BA [56] References Cited UNITED STATES PATENTS.

3,118,973 1/1964 Kasper etal 179/187 YA 3,177,291 4/1965 Porter 179/187 YA r 3,185,772 5/1965 Edstrom 179/18 AB 3,249,699 5/1966 M01 et a1 179/18 AB 3,435,138 3/1969 Borkan 340/166 X 3,465,293 9/ l 969 Weckler 340/166 Primary ExaminerDonald .l. Yusko I Att0rneysC, Cornell Remsen, Jr., Walter J. Baum, Percy P.

Lantzy, J7 Warren Whitesel, Delbert P. Warner and James B. Raden ABSTRACT: An electronic multiselector employs metaloxide-silicon FET transistors in logic circuits comprising NOR gates and inverters. Horizontal selection signals are delivered by a shift register which provides line scanning in a selection stage.

ELECTRONIC MULTISELECTOR The present patent of addition concerns improvements to multiselectors for switching stages in which contacts located at the cross-points are replaced by field-effect transistors and in which the said contacts are maintained in closed position electronically.

It is a well-known fact that field'effect or FET transistors, and in particular, metal-oxide-silicon 'FET transistors or MOS transistors," have interesting characteristics when used as contact elements. In fact, the drain-source resistance of a MOS transistor, which constitutes the switched contact, is strictly voltage controlled so that there is a very good insulation ofthe control circuit with regard to the energized circuit.

Moreover, in this type of transistor, the drain-source re- :lslwlee is higher than if) ohms in the "high-impedance off" state and as low as I to 300 ohms in the "low impedance on state which ensures very good operating characteristics as a contact element.

Another advantage of a multiselector equipped with MOS transistors as contact components lies in the fact that the selection and control circuits can also be designed with MOS transistors, both as regards the active components and the resistors. Consequently, multiselector matrices can be made with a capacity of 4X2, 4X4, 4X8 etc...cross-points in large scale integrated circuits which may comprise several hundred MOS transistors.

The object of the present invention is therefore to realize an elementary electronic multiselector in large scale integrated circuit.

It is a feature of the invention that a switching circuit is located at each cross-point between two perpendicular speech conductors made up of a verticalj and a horizontal k of the multiselector, that said circuit comprises first a contact element made up of a MOS transistor the source and drain of which are connected, respectively to exemplary conductors the verticalj and to the horizontal k and second, a holding flipflop comprising transistors of the same type with its 1 output connected to the switching transistor grid so that, when said flip-flop is in the 1 state, the said transistor is conducting low impedance on" state) which corresponds to the closing of a pair of contacts connecting conductorsj and k.

Another feature of the invention is that an elementary multiselector matrix comprises m verticals and n horizontals with which the same number of selection conductors are associated, that the selection of a particular vertical j is effected by applying a signal Cj to the vertical selection conductor cj, that the selectigg of a particular horizontal k is effected by applying a signal Sk to the horizontal selection conductor sk, that the matrix also comprises n busy state" conductors e1, e2. .ek... en associated with the horizontals, a sign al Ek appearing on conductor ek when at least one contac t is closed to said horizontal, that in the rest position, signals Cj and Sk are applied to the selection inputs to ensure that the position of the holding flipflop remains unchanged and that an inverter circuit to which signal C] is applied delivers a signal C delayed by a time t which is slightly longer than the switching time of the holding flip-flop.

Another feature of the invention is that, in order to close the switching circuit Xjk, first the horizontal lection of the said cross-point is effected by applying signal Sk, second the vertical selection of the said point is effected by applying signal Cj which controls the opening of all the switching circuits associated with verticalj by resetting their holding flip-flops in the 0 state, third signal C] is suppressed and signalC'fsets in the l slate the holding flip-flop of the selected switc hing circuit when signal ii is present. and fourth si nul Sk is suppressed so that the circuit receives signals li and Sk which hold it in rest position.

Another feature of the invention is that the horizontal selection conductors are connected to the corresponding outputs of a shift register into which a code is introduced in series to control the horizontal selection in the matrix.

RDS=

The above mentioned and other features and objects of this invention will become apparent by reference to the following description taken in conjunction with the accompanying drawings in which:

FIG. 1 shows a mode of setting up a speech path in an exchange comprising several selection stages;

FIG. 2 shows a symbolic diagram of a switching circuit;

FIG. 3 shows a diagram of an elementary multiselector matrix;

FIG. 4 shows a detailed diagram of a switching circuit and its associated circuits.

Before describing the invention, the main features and mode of operation of MOS transistors will be reviewed. All the transistors shown in FIG. 1 (with the exception of transistors T1 and T2) and in FIG. 4 are of this type.

A MOS transistor is almost completely symmetrical and the electrodes which operate as drain and source can be inverted without any disadvantages and without modifying its operation when it is used in logic circuits. Nevertheless the manufacturer defines, in the specifications, the electrodes which play the part of drain and source. Consequently, in the figures, the source is symbolized by an arrow as is the emitter of a bipolar transistor.

The operating voltages of a MOS-Ph transistor (type P, enhancement transistor) are defined as follows:

VT threshold voltage;

VD drain voltage;

VG grid voltage.

All these voltages are measured with reference to that of the source (VS=0) and expressed in absolute values. Thus, a MOS transistor is in its high impedance off or blocked" state whenKQKZl It then has a drain-source resistance RDS whose value is practically infinite (approximately 10 ohms).

A MOS transistor is on" when VG VT. It then behaves like a passive resistance whose value is KKKQT T) K being a proportionality factor.

In this case there are two on" regions: the low impedance on" region (or nonsaturated region) when VD .VGVT, with a drain-source resistance RDS of low value (50 to 200 ohms).

the high impedance on" region (or saturated region) when VD: VG-VT, with a resistance RDS of relatively high value. i

If a MOS-Ph transistor has a threshold voltage of VT=4v. and then a voltage VG=0 is applied to it, it becomes blocked. If a voltage VG -24v. and a voltage VD lWt-C!" zero and -20 volts is applied to said transistor, it sets into the on state. In practice, if good linearity of resistance RDS is required, must use lower values of VD. The resistance RDS then has a very low value and the transistor allows bidirectional transfer of analog or digital signals between drain and source.

MOS transistors are also used as resistors. Consequently large scale integrated circuits can be designed, this passive element operation being practicable for both types of conduction. For instance, if the transistor operates in the low impedance on" region with a suitable bias (VD VG-VT) and is connected in series with an inverter MOS transistor, either the voltage VD or the ground voltage appears at the connection common to both transistors depending on whether said inverter transistor is off VGgV T) or on (VG VT).

In the various figures accompanying this description, MOS transistors operating as active components are referenced T" and those operating as load resistors bear the reference R."

It is obvious that the use of MOS transistors as load resistors is only feasible where integrated technology is employed in which case they offer advantages from the point of view of manufacture. However, it is obvious that every MOS transistor referenced R and used as a resistor can be replaced by a conventional resistor of the same value.

We shall first recall with reference to FIG. 1 the mode of setting up a speech path in a switching center comprising, for instance, three selection stages a, b and c. In each of these stages this path uses MOS-Ph transistors Ta, Tb and Te as well as bipolar NPN transistors T1, T2 located at the ends of the path. Control signals Aa, Ab and Ac are applied to the MOS transistors via the inverters bearing the same references. The signals to be transmitted are applied to the input D1 and collected at the output D2, the coupling being effected by the capacitors K1 and K2.

When the grids of transistors Ta, Tb and Te reach ground potential (inverters in position said transistors become blocked. When these grids reach potential U3 (inverters in position I the said transistors may be conducting if transistors T1 and T2 are conducting.

We shall describe the operation in DC of the circuit of FIG. 1 assuming that inverters Aa, Ab and Ac are in position 1. It will be assumed that:

U l=l2 volts;

U 3 30 volts.

The voltage U3 is used, in the circuits of FIG. 4, to set the transistors operating as load resistances in their low impedance on" region.

Transistor T1 is conducting ("low impedance on" region) with a collector current l1E(U2Ul/R1).

Moreover, a potential difference U3 is set up between the grid of transistor Tc and the base of transistor T2 via the high impedance of the interelectrode capacity and the leakage resistance of transistor Tc so that both these transistors conduct. Similarly, transistors Tb and Ta conduct and a current 12 flows through them, as well as through T1, the load resistance of transistor T1 then reaching a value of Re+3RDS, in which Re designates the emitter resistance of transistor T2.

In AC operation transistors T1 and T2 are in common base configuration with a very low input (approximately ohms) and a very high output impedance (approximately l megohm). If a] and a2 are the current gains of these transistors, and i1, 12 the AC input and output currents, one has: i2=al.a2.il. It can therefore be seen that, if high gain bipolar transistors are utilized, the output current differs by only a few percent from the input current and that it is independent from the resistance made up by the saturation resistances of MOS transistors Ta, Tb and Te connected in series. Since the input impedance of transistor T1 has a very low value, input current i1 depends only from the value of resistor R3 which comprises the line impedance. At the output, the load impedance is in parallel with resistor R2 and current i2 is shared by these two components according to their conductances.

The above described circuit only allows for transmission of information in one direction, i.e. from D1 to D2, since the reverse voltage transfer ratio hl2 of bipolar transistors T1 and T2 is very low. To achieve bidirectional transmission, two identical chains equipped with 2 wire-4 wire transformation must be utilized. In each selection stage, each contact element or cross-point comprises then two transistors controlled by the same switch.

FIG. 2 shows a symbolic diagram of such a cross-point designed for matrix assembly. When the cross-point is closed, the speech path is set up, in one direction, between horizontal H] and vertical V'l and, in the other, between horizontal H"l and vertical V"l. To simplify the figure, the group of two horizontals will hereafter bear the reference H1 and the group of two verticals the reference V1.

The cross-point is controlled by signals applied to the following conductors:

horizontal selection conductor s1,

vertical selection conductors cl and c 1;

busy line conductors e1.

Moreover, a conductor all transmits information which characterizes the state of the cross-point, namely whether it is open or closed.

It will be noted that in this figure and in FIGS. 3 and 4, the conductors bear references comprising small letters followed by one or two digits and that they are encircled.

FIG. 3 shows a complete multiselector matrix according to the invention comprising horizontals H1, H2...Hk...Hn and verticals V1, V2...Vj...Vm.

At each cross-point a switching circuit, like that represented in FIG. 2, is situated. Of the said circuits, those which are associated to horizontal H] bear references X11, X21...Xml and those associated to horizontal Hn bear references Xln, X2n...Xmn.

Furthermore, the matrix comprises:

a shift register R comprising n stages the n outputs of which are connected to the horizontal selection conductors sl, s2...sk.... This register is also made with MOS-Ph transistors and can be, by way of an example, a dynamic shift register. Such a register, which comprises clock inputs F1, F2, signal input M and signal output N, enables to control the horizontal selection in the matrix by information applied to input M in series form.

A logic circuit per horizontal, namely, in the case of horizontal H1, circuit G1 comprising NOR circuit 6'] and inverter G"l.

Table I, below, indicates the various signals applied to the control conductors (signals bearing references in capital letters) as well as the corresponding voltage levels and the designation of said signals.

For the purpose of simplification, the references of the conductors and signals, in this table, do not bear the digits identifying the horizontal and the vertical to Whl-il each cell is associated.

As can be seen from the table, a signal of amplitude U2 applied to selection conductor sk characterizes the nonselection of horizontal I-Ik. Moreover, if it is assumed that the signals applied to input M of register R are negative logic signals, as are all the other signals, digits 1 and 0 are characterized by levels U2 and zero respectively.

Consequently, in a matrix comprising, for instance, four horizontals H1 to H4, line H3 is selected by the transmission, in series form, of the binary number 1011.

The circuit G'l delivers a signal Ek of amplitude U2 for the logic condition EI=Al I+A2l+...Aml.

The inverter G"1 delivers a signal E1 of amplitude U2 for the logic condition El=Al l+A2l+...Aml

Signal El therefore indicated that at least one switching circuit associated to the horizontal H1 is closed: it will hereafter be called busy signal.

The connection signal C1 transmitted by the vertical selection conductor c1 to the circuits associated to vertical V is C1) signal Cl remains present for a time t.

H0. 4 shows a detailed diagram o1 one of the switching cir cuits X1 1, X2] etc. .ot'FlG 3 Such a circuit which, is labeled Xjk, comprises the bidirectional cross-point Kjlr, its control circuit comprising the flip-flop A k and the NOR circuit Pjk divided into two parts; the first deals with the effect of the control signals on a nonselected cell and the second describes a specific process for closing the switching circuit Xjk located at intersection between vertical Vj and horizontal Hk.

The figure also shows a detailed diagram of the logic circuit 5 l NORScleCted Cells Gk associated to horizontal Hk and of the delay circuit L as The lines referenced l l. 1.2, 1.3 in table Ill indicate the sociated to the vertical V signals and voltages on conductors c, c, s, e and p (NOR cir- In the circuit Gk, the NOR circuit Gk of FIG. 3 comprises cuit Pjk output, FIG. 4) in the followin". cases the MOS-Pk transistors TI, 7?...Tm connected in parallel and L1 Rest state (table "I, reference 1.1 R6 and the inverter G"k comprises the MOS-Pb t n i tor in the rest state, i.e. when neiiher the opening or closing of T7 and R7. Similarly, the inverter Lj comprises the MOS-Ph circuit Kjk is effected, signals Cj and F; are applied tothe transistors T8 and R8. selection inputs as well as a signal H or Ek. Signal blocks The NOR circuit Pjk which comprises the MOS-Ph the control transistor T5 of the flip-flop Ajk and signals Sk and transistors T9, T10, Tl ll, R9 is identical to the circuit Gk and Cj block the gate Pjk so that the flip-flop is held in position redelivers a preselection signal Pjk of amplitude-U2 for the gardless of the voltage level on conductor ek. logic condition: Pjk=C'j'l-Slt+Elr-Cj. SkEk. It will be noted that, if signal Sk is applied when transistor it can be seen therefore, by referring to table I, that a T5 has been receiving signaljfor at leastaduration 1, signal preselection signal Pjk is only present when the following Cj still blocks gate Pjk,

TABLE III Conductors Ref. Operation c c s c p Flip-flop 1.1 Rest... 6; o] Cj[-U2] Sk [-U2] El; orji; :1? 1.2. Vertical half selectlon.. 2 [-U2] 0 [0] [-U2] E or E T: A 1.3.. Horizontal half selection. C [0] C [-U2] S [O] E or E P 2.1 Horizontal selection 67in] Cj[-U2] @[0] 32cm] 1 22-..... Vertical selection PZPUE] (1210] L [0] 1 :[0] Pjk Ajk 2.3a Closing C j[0] Cj[0] gm] -no 15 Ajk 2.3b Holding Cj [0] I'M-U Sic [0] Ek [-U2] Pjk three conditions are simultaneously fulfilled:

The horizontal Hk is free (conditionETc) The horizontal Hk is selected (condition A delayed connection signal is present (condition C'j).

The cross-point Kjk, located at the intersection of horizontals H, H" and of verticals V, V effects the connection between conductors Hk-V'j and Hk-V"j when the MOS-Pb transistors T12 and T13 are conducting. The control signal Ajk applied to the grids of the said transistors is delivered by the flip-flop bearing the same reference. This holding flip-flop comprises the MOS-Ph transistors T3, T4, T5, T6, R4 and R5.

The operation of such a flip-flop in which transistors T5 and T6 are used to control the switching, is similar to that of a flipflop equipped with PNP bipolar transistors and will not be described in detail.

Table ll, below, indicates the state of transistors T3 and T4 when the flipflop is in the 1 and in the 0 states as well as the state of the cross-point Kjk and the drain voltages of said transistors.

The grids of control transistors T5 and T6 are either brought to potential-U2 (logic c t )rtions Cj, Pjk) or to ground potential (logic conditions Cj, Pjk). it can be seen that, for the logic condition Cj, transistor T5 is conducting and that flip-flop Ajk is set in the 0 state (logic condition A l?) and that, in condition Pjk, it is set in the 1 state (logic condition Ajk).

it will be noted that if transistors T5 and T6 are simultaneously conducting through the application of signals Cj and Pjk, the drains of transistors T3 an d T4 are both brought to ground potential and that a signal Ajk appears.

1.2 Application of a connection signal (table Ill, reference 1.2)

The application of signal Cj on the vertical selection conductor cj produces the opening of all the cross-points associated to the vertical Vj. In fact, said signal makes all transistors T5 conducting and flip'i'lops A are set in the 0 state. Line 1.2 of table 111 represents the various voltages in the case of nonselected horizontals (signal S).

1.3 Application of a selection signal (table III reference 1.3) When the horizontal Hk is selected by applying the signal Sk, the nonselected verticals receive a signal C and, as can be seen, each gate P remains blocked provided that signalfihas l: i applied for at least a time t before signal 2. Closing ofa crossoint There follows a description, given by way of a nonlimitative example, of a process for closing circuit Xjk assuming that the voltages initially applied corresponded to the rest state (table Ill, reference 1.1) and that the horizontal Hk is free, i.e. that a signalTizis standing on conductor ek. The said closing process comprises the following operations carried out in time succession.

2. l Horizontal selection (table [11, ref. 2.)

Signal ltis applied to conductor sk. As signal C j is present, gate Pjk is blocked and flip-flop Ajk does not switch. 2.2 Vertical selection A signal Cj is applied to conductor cj so that flip-flop Ajk resets in the 0 state (condition m). After a delay I, circuit Lj delivers a signal and, if the horizontal is freethis being characterized by the signal fie; signal Pjk appears so that the drains of transistors T3 and T4 are both grounded (table Ill,

u (signal Ki?) There follows a description-with reference to table ll--of ref. 2.2). Transistors T12 and T13 (FIG. 4) are blocked and the operation of the multiselector of HGV 3. This description is the cross2point is still open (condition A712).

2.3 Closing of the cross-potnt The signal is suppressed (condition 6 however signal ("j remains for a time I Transistor T3 is therefore blocked whereas transistor T4 remains conducting under the control of the signal Pjk (table lll, ref 2.3a)

Consequently flip flop Ajk is set in the l state (condition Ajk) making transistors T12 and T13 conducting: the crosspoint is closed and a signal Ek appears which blocks the gate Pjk (signal W). After a time 1, signal Bj is also produced (table lll, ref. 23b): the cross-point is held in a closed position. 2.4 End of operation The signal g is suppressed (condition Sk) and the device is at rest. (table lll ref. 1.1).

While the principles of the above invention have been described in connection with specific embodiments and particular modifications thereof it is to be clearly understood that this description is made by way of example and not as a limitation of the scope of the invention.

in particular, opposite polarity transistors can be used by inverting the polarities of the power supply sources.

We claim:

nected. each cross-point comprising a control circuit including a flip-flop having I and O outputs and incorporating MOS transistors, means coupling the 1 output of each said flip-flop to the grid electrode of an MOS transistor causing it to conduct when the flip-flop is in the 1 state and causing it to block when the flip-flop is in the 0 state 2. An electronic switching circuit as claimed in claim 1, in which there are means individual to each of said first plurality of conductors for resetting the flip-flop by applying a connection signal to its input and an electronic gate is coupled to each of the conductors of said first plurality for setting the flipflop by applying a setting signal when the gate receives signals indicating resetting is in order.

3. An electronic switching circuit as claimed in claim 1 in which the first and second pluralities of conductors in the matrix comprise respectively m verticals and n horizontals with which the respective selection conductors are associated, means coupled to each conductor of said first plurality for ac cepting a signal over a selected horizontal to establish conditions for closure of the corresponding cross-point, said matrix including m delay conductors coupled to the verticals and n busy state conductors coupled to the horizontals and means supplying signals over respective delay conductors and busy state conductors to hold the flip-flop in an unchanged status.

4. An electronic switching circuit as claimed in claim 1, in which there is a shift register commonly coupled to the conductors of said second plurality whereby outputs of said shift register are employed to control selections in the matrix. 

1. An electronic switching circuit comprising a matrix formed by a first plurality of conductors and a second plurality of conductors intersecting at a plurality of cross-points, each cross-point including an MOS transistor having grid and source and drain electrodes, means coupling said source and drain electrodes to conductors which are to be interconnected, each cross-point comprising a control circuit including a flip-flop having 1 and 0 outputs and incorporating MOS transistors, means coupling the 1 output of each said flip-flop to the grid electrode of an MOS transistor causing it to conduct when the flip-flop is in the 1 state and causing it to block when the flip-flop is in the 0 state.
 2. An electronic switching circuit as claimed in claim 1, in which there are means individual to each of said first plurality of conductors for resetting the flip-flop by applying a connection signal to its input and an electronic gate is coupled to each of the conductors of said first plurality for setting the flip-flop by applying a setting signal when the gate receives signals indicating resetting is in order.
 3. An electronic switching circuit as claimed in claim 1 in which the first and second pluralities of conductors in the matrix comprise respectively m verticals and n horizontals with which the respective selection conductors are associated, means coupled to each conductor of said first plurality for accepting a signal over a selected horizontal to establish conditions for closure of the corresponding cross-point, said matrix including m delay conductors coupled to the verticals and n busy state conductors coupled to the horizontals and means supplying signals over respective delay conductors and busy state conductors to hold the flip-flop in an unchanged status.
 4. An electronic switching circuit as claimed in claim 1, in which there is a shift register commonly coupled to the conductors of said second plurality whereby outputs of said shift register are employed to control selections in the matrix. 